6 Conclusion and Future Work

The construction of R, the process encapsulating the timing information, is not as eecient as it could be. Any method for making timing veriication more eecient, such as partial order reductions, could in principle be incorporated into our current scheme. We believe that our work will be useful in applications such as asynchronous circuits and hardware software co-design, where abstract descriptions of systems necessarily include timing information. A all by constructing and verifying a homomorphism as before. We will refer to this as the \overall" abstraction. The Seitz circuit has the property that the center stage can be repeated n times to construct a FIFO queue of length n. Veriication techniques similar to the above can be used to verify such a queue with only a polynomial increase in complexity, contrasted with the exponential dependency of the state space on n. The data from the experiments is listed in Table 1. The homomorphismcheck was performed within Cospan using BDDs as an implicit representation for sets and relations. Cospan has the capability to return a counterexample if the desired relation does not hold. This was instrumental in obtaining a correct abstraction by iteration. Tests were run on an SGI machine with 1 GB memory. To act as a comparison, we attempted to run timed reachability analysis on Num. of Largest timing Num. of loc.s of R BDD nodes CPU time clocks constant (in thousands) (in thousands) (seconds) Input 6 32. Table 1. (Env) denotes the veriication corresponding to equation (3). The same environment abstraction was used for both center blocks. Since timing constants must be integers, a 20% variation in a gate delay of k is represented by specifying the delay to be between 5k and 6k. the complete circuit without using any compositional rules and abstraction. The computation did not complete: the computer ran out of memory after running for several hours. We proposed a framework for hierarchical reasoning about real-time systems. Our framework supports modular and compositional veriication rules. We proved that the problem of checking for timed simulation relations is decidable. On the application side, we generalized the notion of state homomorphisms to timed processes, and gave an algorithm to check if a given map between the locations of two processes preserves timed behavior. The proposed algorithm was implemented in Cospan, and as a case study, we dealt with the Seitz queue circuit. Our experience was that it …